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2D DCT accuracy algorithm architecture array bandwidth block buffer cache calculate clock colour compiled components computational configuration continuous n-tuple classifier crowd monitoring cycles DCT circuits deghoster system developed devices digitised Discrete Cosine Transform edge Electronics Engineers face recognition filter FPGA frame function ghost hardware high performance Hq(Z IEEE Transactions image processing image processing system implementation input instruction word interface IRISC kernel latency mapping match MByte memory module motion detection motion estimation motion vectors multiple Myrinet OpCode operations optical flow output parallel processing PCI bus pipeline pixels PowerPC processing layers programming prototyping re-configuration real-time reduced scaleable search window segmentation sequence shown in Figure SIMD simulation single speed SRAM stage stored structure subsampling subtree taps technique transfer transform transputer tree processor values video signal VLIW VLSI workstation Xilinx