Colloquium on High Performance Architectures for Real-Time Image Processing: Savoy Place, London, Thursday, 12 February 1998IEE, 1998 - Computer architecture |
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1998 The Institution 2D DCT accuracy algorithm applications architecture array bandwidth block buffer cache calculate clock colour communications components computational configuration continuous n-tuple classifier convolution crowd monitoring cycles DCT circuits developed devices digitised Discrete Cosine Transform duplex Electronics Engineers face recognition filter FPGA frame function ghost hardware high performance Hq(Z IEEE Transactions image processing image processing system implementation input instruction word interface IRISC KP LPF latency mapping match MByte memory module motion detection motion estimation motion vectors multiple Myrinet opcode operations optical flow output parallel processing PCI bus pixels PowerPC processing layers programming prototyping re-configuration real-time reduced Savoy Place scaleable search window segmentation sequence SIMD simulation speed SRAM stage stored structure subsampling subtree taps transfer transform transputer tree processor values video signal VLIW VLSI Xilinx