High Speed Computation: Vector ProcessingThe University., 1978 - Vector analysis |
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4-33 S Logical adder address register ALAMOS SCIENTIFIC LABORATORY algorithm APAL APEMAN APTEXT APTLOAD APTRAN compiler APTRAN routine Array Processor assembly language bits block called chain slot channel clock period column computation data flow DECOMP EGGK elements error evaluation exchange package exchange sequence EXEC execution fetch Figure filename flag Floating Point Systems floating-point FLOPS functional unit grid host input instruction buffer integer issue kernel Load loop LU decomposition machine matrix multiply memory references method MFLOPS mode operand operand register outer product output parallel parameters performance pipeline problem processing recurrence result register scalar segments shift simulator solution sparse matrix startup statement step storage stored subroutine SUBTRACTS SV speed Table transfer Transmit tridiagonal vector instruction vector length vector operations vector processor vector registers word XXX XXX XXX zero