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adder addition address register algorithm arithmetic array assembly language bits block buffer buses bytes cache called cell clock communication complex components connected contains control fields control lines control memory control signals control unit coprocessor corresponding counter cycle data transfer decimal decoder defined denotes device digit example execution fetch FIGURE fixed-point flip-flop floating-point floating-point number format function gate hardware hypercube implemented input instruction pipeline instruction set interconnection interrupt request language logic circuit machine main memory mantissa memory address microinstruction microoperations microprocessor microprogram Multibus multiplexer multiplication multiprocessor nodes opcode operands operating system output parallel performance physical address pipeline processor program counter queue read-write represent result segment sequence sequential shift shown in Fig specified stack storage stored structure subroutine subtraction switching system bus tion twos-complement typical values vector vector processors word zero