Proceedings, ... International Symposium on VLSI DesignIEEE Computer Society Press,., 1997 - Electronic digital computers |
Contents
MONDAY KEYNOTE ADDRESS | 5 |
A Parallel Genetic Algorithm Approach | 27 |
SYNTHESIS | 45 |
Copyright | |
27 other sections not shown
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Common terms and phrases
adder algorithm analog analog circuits application approach architecture array assignment asynchronous benchmark Berger code binary bits block Boolean cache capacitance cell chip clock CMOS coefficients components Computer Computer-Aided Design Conf constraints cost cycle datapath decoder delay faults detected edge encoding evaluation fanout fault coverage fault simulation filter finite state machine flip-flops floorplan FPGA function gate genetic algorithm graph hardware IEEE IEEE Trans implementation India input interconnect linear logic logic synthesis machine memory method minimization module multiple node op-amp operation optimal output overhead pair parallel partitioning path delay performance placement problem Proc procedure processor proposed reconfigurable reduced reset ROBDD scan scheme Section sequence sequential circuits signal speedup step stuck-at switching synthesis Table techniques Technology test set testability tion transistors transition variables verification VLSI Design 96 voltage Xilinx Xputer