TRON Project 1990: Open-Architecture Computer SystemsKen Sakamura I wish to extend my warm greetings to you all on behalf of the TRON Association, on this occasion of the Seventh International TRON Project Symposium. The TRON Project was proposed by Dr. Ken Sakamura of the University of Tokyo, with the aim of designing a new, comprehen sive computer architecture that is open to worldwide use. Already more than six years have passed since the project was put in motion. The TRON Association is now made up of over 140 co m panies and organizations, including 25 overseas firms or their affiliates. A basic goal of TRON Project activities is to offer the world a human-oriented computer culture, that will lead to a richer and more fulfilling life for people throughout the world. It is our desire to bring to reality a new order in the world of computers, based on design concepts that consider the needs of human beings first of all, and to enable people to enjoy the full benefits of these com puters in their daily life. Thanks to the efforts of Association members, in recent months a number of TRON-specification 32-bit microprocessors have been made available. ITRON-specification products are continuing to appear, and we are now seeing commercial implementations of BTRON specifications as well. The CTRON subproject, mean while, is promoting standardization through validation testing and a portability experiment, and products are being marketed by sev eral firms. This is truly a year in which the TRON Project has reached the practical implementation stage. |
Contents
| 3 | |
Considerations of the Performance of a RealTime | 25 |
Dynamic Stepwise Task Scheduling Algorithm | 43 |
A Graphical Debugger for | 63 |
A μITRONSpecification Realtime Operating System | 85 |
KOBAYAKAWA T NAGASAWA T SHIMIZU | 99 |
A Study on a Hypermedia Editor on BTRON1 Specification | 119 |
CTRON Software Portability Evaluation | 132 |
Design Considerations of OnChipType FloatingPoint Units | 235 |
The Design Method of High Speed Cache ControllerMemory | 249 |
Inline Procedures Boost Performance on TRON Architecture | 275 |
A Forth Kernel for Gmicro | 293 |
The GMICRO Microprocessor and the ATT UNIX | 311 |
Implementation of Symbolic ROM Monitor | 325 |
Performance Evaluation of TOXBUS | 346 |
Realtime OS TR90 Based on MicroITRON Specification | 377 |
Table of Contents | 149 |
OS Subset Structure Achieving AP Portability | 173 |
An Evaluation Method of Kernel Products Based on CTRON | 191 |
Implementation and Evaluation of Oki 32bit | 221 |
Communication Terminal for Heterogeneous Network | 391 |
Pitfalls on the Road to Portability | 409 |
Realization of the MicroCTRON Kernel under PSOS+ | 427 |
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Common terms and phrases
algorithm application programs architecture Basic bitmap BMail BTRON1 specification bytes cache data clip video clock cycles command Communication Control compiler configuration CTRON data memory debugging defined device display dynamic Electric entry environment evaluation event flag execution Extended OS programs Figure floating-point functions GMICRO hardware Hitachi host hostcap hypermedia IEEE implementation inline procedure instruction INTERACTIVE interface unit interrupt handler interrupt latency ISDT ITRON Japan Ken Sakamura kernel language layer load machine memory management microprocessor Mitsubishi Electric Corporation modules multiprocessor Oki Electric Industry operand operating system parameters performance porting priority procedure inlining processing processor protocol queue real object real-time registers Sakamura scheduling shared memory signal software portability stack subset synchronization system bus Table target task switching task switching latency Tokyo TOXBUS TRON Association TRON Project UNIX System user program