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analytic model arithmetic pipeline arithmetic unit ASC 1-pipe ASC instruction average service benchmark block branch Buffer limit components computer architectures Cray Research CRAY-1 architecture CRAY-1 model described determine developed distribution of service double buffers eliminated execution unit level execution unit modeling execution unit service execution unit structure fetch delay fixed point add floating point multiply floating point units fork Junction Fortran functional unit hardware hierarchy of models implementation instruction buffers instruction execution instruction format instruction sequence table instruction stream instruction trace instruction types level models lookahead queue machines MBU-AU memory fetch MODELING FOR PARALLEL-PIPELINE monitor routine operand retrieval parallel PARALLEL-PIPELINE CENTRAL PROCESSORS performance pipeline execution unit pipeline units predict presimulation queuing network model queuing network simulations register file register update scalar service delay service routine shown in Figure simulation model structural simplifications Texas Instruments throughput trace-driven simulation utilization validated vector instructions vector processing weighted constant average