Modeling for Parallel-pipeline Central Processors |
Common terms and phrases
ACM Computing Surveys active add instruction analytic model arithmetic pipeline arithmetic unit ASC 2-pipe ASC architecture average service benchmark block branch Buffer limit CDC CYBER components computer architectures condition code Cray Research CRAY-1 architecture CRAY-1 model defined described determine developed distribution of service double buffers eliminated execution unit level execution unit modeling execution unit service execution unit structure fixed point add floating point multiply fork junction Fortran functional unit hardware instruction buffers instruction execution instruction format instruction sequence table instruction stream instruction trace instruction types level models lookahead queue machines MBU-AU memory fetch monitor routine operand retrieval parallel PARALLEL-PIPELINE CENTRAL PROCESSORS pipeline execution unit pipeline units predict presimulation queuing network model queuing network simulations register file register update scalar service routine shown in Figure simulation model specified structural simplifications Texas Instruments throughput TI ASC trace-driven simulation utilization validated vector instructions vector processing