Analog-digital simulation of transient-induced logic errors and upset susceptibility of an advanced control system
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2100 transient injections 9 pC Analog-Digital Simulation approximately Carreno cessor charge level Circuit Analysis CMOS Computer control loop control unit countdown decoder unit describes a simulation digital simulation Digital System electrical transients produce error propagation error recovery techniques Figure first-order errors first-order latched errors Functional errors functional units gate-level description gate-transistor Hamilton Standard IEEE IEEE Trans Illinois implemented incorporates fault-tolerant techniques Injection node injections are analyzed integrated circuit intermodule Langley Research Center large-scale integrated logic values memory Micropro microprocessor monitoring multiplexer NASA nsec order errors output parity percent Performing Organization program flow analysis R. K. Iyer recovery mechanisms Research Center Hampton Results for 2100 sient injection simulation run software testing study of upset system being tested system under test system upset tems three gate distances Transient-Induced Logic Errors Transient-injection process transistor level Transistor models type of error upset mode Upset Susceptibility upset testing watchdog and control watchdog unit