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Efficient Computation of Buffer Capacities
Wiggers University of Twente M Bekooij Philips Research
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abstraction accelerator algorithm allows analysis application approach architecture average benchmarks block buffer channel checking clock combination communication compiler complexity components Computer configuration connected consider constraints consumer consumption copies core cost cycles delay depends described determine distributed dynamic embedded systems encoding energy error example execution exploration Figure flow function given graph hardware IEEE implementation improvement increase input instructions International latency loop mapping memory method multiple node on-chip operations optimization output parallelism parameters partitioning path performance period phase pipeline platform port presented problem processor producer proposed real-time reduce represents router routing running scheduling selected shared shown shows SIMD simulation single solution space specific stage step synthesis Table task technique threads tion tool traffic transaction University Xtensa