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A Yu and T
INCREASING DESIGN QUALITY AND ENGINEERING PRODUCTIVITY THROUGH
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30th ACM/IEEE Design ACM copyright notice algorithm analysis approach assignment behavioral binary block Boolean functional bound cell clock combinational Computer-Aided Design Conf constraints cost critical path delay model denote Design Automation Conference detected edge efficient Elmore delay example experimental results fanout fault coverage fee and/or specific Figure finite state machine flip-flops FPGA gate g graph hazards heuristic IEEE implemented independent fault sets initial iteration latches layout logic module logic synthesis LUTs maximum method minimization minimum operation optimization output parameters partial scan partitioning performance primary inputs problem Proc procedure processors rectilinear Steiner tree reduce routing Section selected sensitizable sensitization sequence sequential circuits shown signal simulation skew solution spanning tree Steiner tree synthesis system Table techniques technology mapping test pattern test set test vectors Theorem tion transition traversal variables verification VHDL VLSI wire worst-case Xilinx