Studies of InAIAs/InGaAs and GaInP/GaAs Heterostructure FET's for High Speed Applications |
What people are saying - Write a review
We haven't found any reviews in the usual places.
Contents
Ga0 511n0 49PGaAs HETEROSTRUCTURE DEVICES | 11 |
LOWFREQUENCY NOISE AND FREQUENCY DISPERSION | 50 |
PCHANNEL InAlAsIng Ga1xAs x 0 53 0 65 STRAINED | 65 |
3 other sections not shown
Common terms and phrases
activation addition AlGaAs/GaAs HEMT's approach band bias buffer carriers causes channel characteristics charge circuits compared conduction corresponding decreases deep traps demonstrated density dependence designs directions discussed dispersion doped Drain-source current Drain-source voltage dual-channel E/D-mode effects Electron Device enhancement evaluated excess fabricated FET's Figure followed frequency Ga1-xAs GaAs gain GaInP/GaAs gate gate bias gate voltage HEMT's heterostructures HIGFET's higher hole IEEE impact implant improvement InAIAs InAlAs/InGaAs InAlAs/InGaAs HIGFET's increase InGaAs integrated inverter ionization Isub lattice matched layer leakage Lett logic material maximum measurements MICHIGAN microwave mobility mS/mm noise observed obtained operation orientation output p-channel performance present reduced region reported resistance respectively Schottky shift shown in Fig shows sidegating similar strained stress structure substrate subthreshold suggests temperature tests thickness threshold voltage transconductance transfer undoped values versus
Bibliographic information
| Title | Studies of InAIAs/InGaAs and GaInP/GaAs Heterostructure FET's for High Speed Applications |
| Author | Yi-Jen Chan |
| Publisher | University of Michigan., 1992 |
| Original from | the University of Michigan |
| Digitized | Mar 26, 2011 |
| Export Citation | BiBTeX EndNote RefMan |