What people are saying - Write a review
We haven't found any reviews in the usual places.
Overview of the 80960KB LBus
Timing Generation 314
7 other sections not shown
16-bit data 80960KB CPU Programmer's 80960KB processor address decoder address latches address lines arbitration Arrow Electronics asserting HLDA BADAC burst logic burst transaction bus master byte enable signals clock cycle column address control logic control signals CPU Programmer's Reference CYCLE-IN-PROGRESS data bus data flow data lines data transceivers data transfer data word deasserted Diagram DRAM controller DT/R edge of CLK2 EPROM external interrupt controller HLDAR HOLDR I/O devices IAC message IAC pin input pin instructions INT0 INT2 Intel Corp interface circuit interrupt acknowledge Interrupt Control register interrupt request interrupt signals interrupt vector INTR L-bus memory interface message buffer multiplexed output signal peripheral device precharge processor clock cycle Programmable Interrupt Controller Programmer's Reference Manual read operation read transaction READY signal READY0 remains asserted RESET signal rising edge self-test Serial Communication shown in Figure signal indicates SRAM Synchronous write operation write transaction