80960KB Hardware Designer's Reference Manual |
Contents
Overview of the 80960KB LBus | 3-1 |
LBus Transactions | 3-8 |
Timing Generation 314 | 3-14 |
7 other sections not shown
Common terms and phrases
16-bit data 80960KB CPU Programmer's 80960KB processor address decoder address latches address lines arbitration Arrow Electronics bits burst logic burst transaction bus master byte enable signals CLK2 CLK clock cycle column address control logic control signals CPU Programmer's Reference CYCLE-IN-PROGRESS data bus data lines data transceivers data transfer data word deasserted Diagram DRAM controller DRAM-RDY Drive DT/R edge of CLK2 EPROM external interrupt controller Hamilton/Avnet Electronics HLDA HLDAR HOLDR I/O devices IAC message IAC pin input pin input signal instructions INT3 Intel Corp interface circuit Interrupt Control register interrupt request interrupt signals interrupt vector INTR L-bus message buffer multiplexed output signal Pioneer Electronics processor clock cycle Programmable Interrupt Controller Programmer's Reference Manual read operation read transaction READY signal RESET signal rising edge Road self-test shown in Figure SRAM SRAM-OE Suite Synchronous throughput delay USER RESET write operation write transaction