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Design Techniques with
Sequential Circuit Design
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Abs.L Abs.W ADDR Addressing category addressing mode arithmetic asserted Binary code Boolean bus error bus master byte BYTE2 clock Computer condition codes connected d(An d(An,Xn Data alterable data bus data register data transfer decimal decoder Design Dest device Digital System DTACK Englewood Cliffs Example exception processing Excess-3 executed external flip-flop full adder function given in Figure H H H H hardware implementation input Intel Corporation interrupt request Karnaugh map Label OPCODE Operand latch least significant load loop memory location microprocessor minterms MMMRRR Motorola Inc OPCODE Operand Comments output performed peripheral permission of Motorola port Prentice-Hall priority processor program counter register pair Reprinted with permission reset rotated sequence sequential circuit shift shown in Figure signal significant bit source operand specified stack pointer status register stored subroutine subtraction sum-of-products supervisory switch synchronous tion transition table truth table variables word zero