A Multiprocessor Architecture for Real-time Control Applications |
Contents
DIGITAL CONTROL ALGORITHMS | 6 |
MULTIPROCESSOR ARCHITECTURE | 10 |
PROCESSOR CONTROL SOFTWARE | 25 |
2 other sections not shown
Common terms and phrases
accelerometer algorithm of Figure arbitration bandwidth required chapter common bus architecture common bus system common memory computer system Control Software Structure CORNELL UNIVERSITY LIBRARIES CPU 2 CPU criteria DATA MEMORY digital control algorithms direction cosine matrix Effective Throughput Tp efficient enter the kernel failure-effect characteristics fault tolerance functions gyros Ideal N*Tp implement individual processor inertial frame inertial navigation systems inertial reference frame input data instruction prefetching interrupt Kernel Interference kernel references low cost MacMinn modularity multi-microprocessor system multiprocessor system navigation coordinate system newer microprocessors number of processors pipeline system processor module processor system program memory Proposed System Read Only Memory real-time computation real-time control applications redundancy management reliability section 3.2 shown in Figure Software resources Standard Common Bus Strapdown Navigation System strapdown system system of section system performance system resources task TASK SWITCH test-and-set Total System Throughput vector vehicle attitude velocity and position virtual processor worst-case throughput απ नै