Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, Volume 17Kluwer Academic Publishers, 1997 - Integrated circuits |
Contents
A Unifying LatticeBased Approach for the Partitioning | 21 |
A Linear Systolic Array for RealTime Morphological Image | 43 |
Mapping of Trellises Associated with General Encoders onto | 57 |
Copyright | |
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algorithm applications architecture bandwidth bit rate bit-rate block matching buffer bytes cell clustering codebook codec coefficients communication compression computation concatenation constraints CYCLE CYCLE-PATH data flow decoder decomposition denoted dilation displacement vector encoder example feedback field FIFO Figure FIR filter function graph hardware HDTV IEEE IEEE Trans Image Processing implementation index point input interconnection iteration lattice layer linear LPGS LSGP macroblock mapping matrix memory method methodology MJPEG motion compensation motion estimation motion features motion vectors MPEG node open box operations optimal P-frame parallel partitioning PATH bits pels performance pipelined pixel PPSFs prediction problem Proc proposed PSNR quadtree queue result scheduling scheme search range Section segmentation sequence shown in Fig space-time spatial standard structure subarrays subbands subdomain sublattice systolic array target array techniques tile tion transformation trellis URE's vector quantization video coding Viterbi algorithm VLSI VLSI Signal Processing