Formal Equivalence Checking and Design DebuggingFormal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail. The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors. From the Foreword: `With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.' Kurt Keutzer, University of California, Berkeley |
Contents
Introduction | 1 |
EQUIVALENCE CHECKING | 11 |
X | 21 |
Incremental Verification for Combinational Circuits 39 | 38 |
Incremental Verification for Sequential Circuits | 61 |
A Local BDDbased Equivalence Verifier | 91 |
Algorithm for Verifying Retimed Circuits | 111 |
RTLtoGate Verification 123 | 122 |
Other editions - View all
Formal Equivalence Checking and Design Debugging Shi-Yu Huang,Kwang-Ting (Tim) Cheng No preview available - 2012 |
Formal Equivalence Checking and Design Debugging Shi-Yu Huang,Kwang-Ting (Tim) Cheng No preview available - 1998 |
Common terms and phrases
3-valued logic simulation 3-valued safe replaceability a₁ algorithm AQUILA ATPG back-substitution backward justification process benchmark circuits Boolean function C₁ candidate equivalent candidate internal pairs candidate list candidate NS-pair candidate pair Chapter characteristic function correction cutset Definition denoted discrepancy function distinguishing sequence equiv equivalence checking equivalent pairs erroneous vector error diagnosis example existential quantification exists an input false candidate fanin fanout fault simulation finite state machine FSM traversal gate gate-level heuristic identifying equivalent implementation incremental verification injection input vector iteration Lemma logic gate logic value M₂ miter next-state node optimized output responses permissible pair present state lines primary inputs primary output pair reachable recursive learning reduced model reset retimed circuits s₁ sequential circuits sequential hardware equivalence sequentially equivalent shown in Fig signal ƒ signal pair similarity single-fix signal smoothed transition relation Strongly Connected Component stuck-at-0 fault symbolic approaches t₁ techniques time-frame transformation unreachable Y₁