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Interrupt Organization 310
Local Bus States 316
Bus Usage 323
17 other sections not shown
286 local bus 82288 Bus Controller 82289 Bus Arbiter address access address decode address latches address lines address mode address strobe bank buffered bus contention bus cycle bus interface bus master bus operation Bus Unit CENL chip selects circuit CLK cycles CMDLY command delays configuration data bus Data Channel data setup data transceivers delay max DT/R dual-port memory dynamic RAM edge of CLK enable EPROMs execution falling edge HLDA I/O devices iAPX 286 system iAPX 86 inactive Intel Interrupt Controller interrupt request interrupt-acknowledge INTR maximum memory and I/O memory devices memory subsystem memory-mapped I/O Multibus non-maskable interrupt operand parameters PCLK performance port prefetch privilege level processor clock protected mode READY input real address mode refresh RESET selector shown in Figure SRDY status strobe logic synchronous system bus system clock task Task State Segment transceivers write cycle write operations