Proceedings, International Test Conference 1997 |
Common terms and phrases
algorithm analog analysis applied area overhead array ATPG boundary scan bridging fault capacitance cell chip circuit circuitry clock CMOS column compression Computer contactor core cost cycle debug defect delay fault device diagnosis error example failure fault coverage fault injection fault model fault simulation flip-flop FPGA frequency functional gate H-SCAN hardware IDDO IDDQ test IEEE implemented input Integrated Circuits interconnect International Test Conference JTAG latch leakage LFSR logic measurement memory method module nodes operation output Paper parameters performance primitive faults probe probe card Proc processor random scan chain selected self-test sequence shown in Figure signal signature SRAM stuck-at fault synthesis Table technique Test Conf test data test patterns test point test program test set test strategy test system test vectors testability tester tool transistor VLSI voltage wafer waveform