Verilog HDL

Front Cover
Prentice Hall, Jan 16, 2003 - Computers - 496 pages
1 Review
A complete Verilog HDL reference which progresses from the basic Verilog concepts to the most advanced concepts in digital design, from gate, RTL and behavioural modelling to timing simulation, switch level modelling, PLI and logic synthesis.

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Review: Verilog Hdl [With CDROM]

User Review  - John - Goodreads

This book is great, I read it cover to cover over a weekend before taking a Verilog class in grad school and it was a great leg up for the class. It has also been a valuable reference at work. Read full review

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About the author (2003)

About the Author

Samir Palnitkar is a recognized authority on Verilog HDL, modeling, verification, logic synthesis, and EDA-based methodologies in digital design. He has worked extensively with design and verification on various successful microprocessor, ASIC, and system projects. He was the lead developer of the Verilog framework for the shared memory, cache coherent, multiprocessor architecture, popularly known as the UltraSPARCTM Port Architecture, defined for Sun's next generation UltraSPARC-based desktop systems. Besides the UltraSPARC CPU, he has worked on a number of diverse design and verification projects at leading companies including Cisco, Philips, Mitsubishi, Motorola, National, Advanced Micro Devices, and Standard Microsystems.

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