Superscalar Microprocessor DesignThe term superscalar describes a computer architecture that achieves performance by concurrent execution of scalar instructions. Superscalar architectures represent the next step in the evolution of microprocessors. This book is intended as a technical tutorial and introduction for engineers & computer scientists. The book concentrates on reduced instruction set (RISC) processors. |
Common terms and phrases
a_ptr Address Unit algorithm allocation antidependencies architecture basic block branch delay branch prediction central window chapter CISC computation consth data cache dataflow decoded instructions dispatch stack example execution fetch floating-point fmul four-instruction decoder functional units future file hardware implementation in-order issue initiation interval instruction decoding instruction parallelism instruction runs instruction set instruction window instructions per cycle large number latencies loads and stores logic lookahead loop iterations low h-mean high memory microcode mispredicted branch Number of Entries number of instructions operands operations out-of-order issue output dependencies pending update performance ports reduced register allocation register file register renaming register update unit reorder buffer reorder-buffer entry requires reservation stations resource conflicts restart result buses result tags RISC RISC processors scalar processor scoreboarding software pipelining software scheduling Speedup 3 low stalls storage conflicts store buffer struction superpipelined superscalar processor tion tmp1 tmp2 trace scheduling troff true dependencies unrolled VLIW yacc