Introduction to Switching Theory and Logical DesignFor upper-level undergraduate courses. |
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1-cubes ABCD assignment assume B₁ binary number binary-coded decimal bits Boolean algebra C₁ Chapter circuit of Fig clock mode clock period clock pulse column combinational logic compatibility class complete connected consider control sequence corresponding cost counter decimal decoder delay Determine diagram digital systems don't-cares elements entries equations equivalence classes essential hazard example excitation maps expression FIGURE function fundamental mode given in Fig implication table input change input sequence integrated circuit inverter J-K flip-flop K-map Karnaugh map level mode logic circuits maximal compatibles maxterm memory minterms mode circuits next-state output pairs parity checker partition possible prime implicants primitive flow table problem q₁ qv+1 reader realization reset result sequential circuit shown in Fig signal single specified stable standard switching table of Fig Theorem transistor transition table truth table truth-functional values variables voltage X₁ Y₁ Y₂