Hot-Carrier Reliability of MOS VLSI Circuits
Springer Science & Business Media, Jun 30, 1993 - Technology & Engineering - 212 pages
As the complexity and the density of VLSI chips increase with shrinking design rules, the evaluation of long-term reliability of MOS VLSI circuits is becoming an important problem. The assessment and improvement of reliability on the circuit level should be based on both the failure mode analysis and the basic understanding of the physical failure mechanisms observed in integrated circuits. Hot-carrier induced degrada tion of MOS transistor characteristics is one of the primary mechanisms affecting the long-term reliability of MOS VLSI circuits. It is likely to become even more important in future generation chips, since the down ward scaling of transistor dimensions without proportional scaling of the operating voltage aggravates this problem. A thorough understanding of the physical mechanisms leading to hot-carrier related degradation of MOS transistors is a prerequisite for accurate circuit reliability evaluation. It is also being recognized that important reliability concerns other than the post-manufacture reliability qualification need to be addressed rigorously early in the design phase. The development and use of accurate reliability simulation tools are therefore crucial for early assessment and improvement of circuit reliability : Once the long-term reliability of the circuit is estimated through simulation, the results can be compared with predetermined reliability specifications or limits. If the predicted reliability does not satisfy the requirements, appropriate design modifications may be carried out to improve the resistance of the devices to degradation.
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OXIDE DEGRADATION MECHANISMS IN MOS TRANSISTORS
MODELING OF DEGRADATION MECHANISMS
MODELING OF DAMAGED MOSFETs
TRANSISTORLEVEL SIMULATION FOR CIRCUIT RELIABILITY
FAST TIMING SIMULATION FOR CIRCUIT RELIABILITY
MACROMODELING OF HOTCARRIER INDUCED DEGRADATION IN MOS CIRCUITS
CIRCUIT DESIGN FOR RELIABILITY
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amount of hot-carrier approach bias conditions bond-breaking current capacitance channel length channel region charge pumping charge trapping circuit reliability circuit simulation circuit-level CMOS inverter Computer-Aided Design damaged MOSFET degra degradation levels degradation mechanisms device model drain current drain end drain voltage dynamic degradation electric field Electron Devices electron injection electron mobility electrons and holes equation Figure function gate current gate oxide gate voltage hot-carrier damage hot-carrier degradation hot-carrier effects hot-carrier induced damage hot-carrier induced degradation hot-carrier induced oxide hot-carrier injection hot-carrier reliability hot-carrier stress hot-electron IEEE IEEE Trans ILLIADS-R impact ionization injection current input signal integrated circuits interface trap inverter stage kinetic energy lateral electric field linear long-term reliability macromodel model parameters MOSFET nMOS transistor output voltage oxide charge oxide degradation pMOS saturation region scaling factor silicon simulation results stress conditions substrate current threshold voltage tion transconductance trapped charge VDSAT voltage waveforms waveforms Wn/CL