ProceedingsComputer Society Press of IEEE, 2002 - Computer architecture |
Contents
Multiprocessor Synchronization and Speculation | 3 |
Applying ThreadLevel Speculation to Explicitly Parallel | 18 |
System Performance and Optimization | 43 |
Copyright | |
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adaptation algorithm applications average bank base basic block behavior benchmarks BHSR bits branch branch prediction buffer bytes cache line cache miss client cluster compiler Computer Architecture configuration constraints content prefetcher critical section currentcy cycles data cache disk dynamic energy entry evaluate execution Figure function global graph gzip hardware hotline I-block IEEE implementation input port instruction window interface data cache kernel latency load lock lock-free loop Maté misprediction multiple network interface network interface data nodes operand operating system optimization output port overhead packet parallel path performance pipeline pointer port arbiters pre-execution threads prediction predictor prefetch Proceedings processor protocol reduce request requires router scheduling script segment sensor networks server shared shows speculative execution speculative thread SRPC stack static StreamIt superscalar Table techniques temporal silence TinyOS tion transaction update useless instructions ZebraNet