ESD in silicon integrated circuits
* Examines the various methods available for circuit protection, including coverage of the newly developed ESD circuit protection schemes for VLSI circuits.
* Provides guidance on the implementation of circuit protection measures.
* Includes new sections on ESD design rules, layout approaches, package effects, and circuit concepts.
* Reviews the new Charged Device Model (CDM) test method and evaluates design requirements necessary for circuit protection.
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Physics and Operation of ESD Protection Circuit Elements
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15th EOS/ESD Symposium advanced CMOS Amerasekera avalanche breakdown behavior BiCMOS bipolar transistor breakdown voltage capacitance channel length chip circuit design CMOS CMOS processes current path damage dependence diffusion resistor diode Duvvury effective Electron Dev Electrostatic Discharge emitter EOS/ESD Symposium Equation ESD Association ESD current ESD event ESD failure ESD performance ESD protection circuits ESD robustness ESD stress failure mode failure threshold gate oxide GCNMOS high current I/O pad IEEE increase injection input protection integrated circuits JEDEC latchup layout LNPN MLSCR MOSFET n-well negative resistance nMOS device nMOS transistor operation output driver parameters parasitic bipolar pMOS polysilicon polysilicon resistor power supply Proc protection design protection device protection elements protection scheme pulse region resistor second breakdown semiconductor shown in Figure silicided silicon simulation snapback stress current substrate temperature tester thermal trigger voltage turn-on waveform width