Alpha Architecture Reference ManualAlpha Architecture Reference Manual, Third Edition is the authoritative reference on the definition of Alpha architecture. Revised by the Alpha Architecture Committee, this book contains a complete description of the common architecture required of all implementations and describes the interfaces to support the Windows NT, Digital UNIX, and OpenVMS operating systems. The third edition reflects the latest implementations of the architecture, including the 21164A, 21164PC, and 21264. Some of the extensions to the architecture and the enhancement to the technical content include: new byte and word load, store and sign-extend operations; new multimedia instructions; new population enumeration and floating-point square root instructions; new instructions to improve data cache efficiency and updated Windows NT section. The Alpha chip is the fastest chip on the marketplace today. It runs Windows NT, UNIX and OpenVMS operating systems. New base-level server configurations provide four times the memory of current systems. Contains updated Windows NT section to reflect current technical port to Alpha Includes new insights into the software aspects of the implementation Covers new multimedia instructions for increased performance with high-end graphics applications |
Contents
Introduction I | 1-1 |
Chapter 2 | 2-1 |
Instruction Formats I | 3-1 |
Instruction Descriptions I | 4-1 |
יייייייין | 4-61 |
413 Multimedia Graphics and Video Support | 4-151 |
System Architecture and Programming | 5-1 |
Common PALcode Architecture I | 5-31 |
55 PALcode Support | 3-25 |
| 4-1 | |
Windows NT Software IIC | 4-5 |
Contents | 4-7 |
Chapter 1 | 4-11 |
Chapter 2 | 21 |
Chapter 3 | 31 |
Exceptions Interrupts and Machine Checks II | 38 |
Console Subsystem Overview I | 5-39 |
InputOutput Overview I | 5-41 |
| 5-42 | |
OpenVMS Alpha Software IIA | 3 |
Contents | 5 |
Introduction to OpenVMS Alpha IIA | 11 |
Chapter 2 | 2-1 |
21 Unprivileged General PALcode Instructions | 2-3 |
23 Unprivileged Queue PALcode Instructions | 2-29 |
25 Unprivileged PALcode Thread Instructions | 2-79 |
Memory Management IIA | 3-1 |
311 Memory Management Faults | 3-13 |
Chapter 4 | 3-15 |
Internal Processor Registers IIA | 5-1 |
Exceptions Interrupts and Machine Checks II | 6-1 |
OpenVMS Alpha Software Index | 6-38 |
Contents | 6-38 |
Introduction to DIGITAL UNIX IIB | 11 |
PALcode Instruction Descriptions IIB | 16 |
The clear floatingpoint enable clrfen instruction | 16 |
See Console Interface Architecture for information on using this | 16 |
Chapter 3 | 16 |
Process Structure IIB | 16 |
Exceptions and Interrupts IIB | 16 |
Chapter 5 | 4-20 |
52 Unprivileged PALcode Instructions | 5-45 |
Initialization and Firmware Transitions IIC | 61 |
| 1 | |
Chapter 2 Console Interface to Operating System Software | 3 |
Contents | 5 |
Console Subsystem Overview III | 11 |
Console Interface to Operating System Software III | 2-1 |
System Bootstrapping III | 3-1 |
| 1 | |
Appendixes | |
Contents | |
Software Considerations | 1 |
IEEE FloatingPoint Conformance | 17 |
B2 Alpha Support for OS Completion Handlers | 3 |
Instruction Summary | 1 |
C7 OpenVMS Alpha PALcode Instruction Summary | 14 |
C13 Opcodes Reserved to DIGITAL | 21 |
Registered System and Processor Identifiers | |
Waivers and ImplementationDependent | 1 |
| 23 | |
| 2-1 | |
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Common terms and phrases
address space aligned Alpha architecture arithmetic trap bits block bootstrap byte cache CALL_PAL console terminal counter denormal Description DIGITAL UNIX disabled enable endif environment variable exception execution fault field FIXUP flag floating-point Floating-point Operate FPCR function code GPR State Change halt handler hardware header HWPCB HWRPB I/O device Illegal Instruction illegal operand implementation-specific initialization Instruction mnemonics integer overflow internal processor register interprocessor interrupt interrupt request kernel mode kernel stack load Longword Queue mapping memory barrier memory management offset Opcode OpenVMS OpenVMS Alpha operand Operate format operating system page table PALcode format PALcode instructions per-CPU slot performance physical address primary processor register Quadword Queue restart result routine secondary interlock Section sequence software interrupt specified stack pointer Swap system software T_floating tmp1 tmp2 Translation Buffer underflow UNPREDICTABLE virtual address Windows NT write zero
References to this book
Computer Architecture: A Quantitative Approach John L. Hennessy,David A. Patterson No preview available - 2003 |