## Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical Circuits in Computers and Discrete Systems'Et moi ... ~ si j'avait su comment en revenir. One service mathematics has rendered thl je n'y serais point aile: human race. It has put common sense back where it belongs. on the topmost shelf nexl Jules Verne to the dusty canister labelled 'discarded non· The series is divergent; therefore we may be sense'. Eric T. Bell able to do something with it O. Heaviside Mathematics is a tool for thought. A highly necessary tool in a world where both feedback and non· Iinearities abound. Similarly, all kinds of parts of mathematics serve as tools for other parts and fO! other sciences. Applying a simple rewriting rule to the quote on the right above one finds such statements as: 'One service topology has rendered mathematical physics .. .'; 'One service logic has rendered com· puter science ... '; 'One service category theory has rendered mathematics .. .'. All arguably true. And all statements obtainable this way form part of the raison d'etre of this series. |

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### Contents

Asynchronous processes and their interpretation | 12 |

Selfsynchronizing codes | 43 |

Aperiodic circuits | 64 |

Circuit modelling of control flow | 114 |

Composition of asynchronous processes and circuits | 189 |

The matching of asynchronous processes and interface organization | 215 |

Analysis of asynchronous circuits and processes | 243 |

### Other editions - View all

Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical ... Victor I. Varshavsky No preview available - 1990 |

Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical ... Victor I. Varshavsky No preview available - 2011 |

### Common terms and phrases

analysis anomalous antitonous aperiodic circuits arbiter asynchronous circuits asynchronous process balanced code behaviour binary Boolean Boolean functions called checker circuit of Fig code combinations combinational circuit complement completion constructing corresponding defined DEFINITION delay-insensitive denoted double-rail encoding equations equivalence class example excitation functions Figure finite state machine flip-flop fragments gate delays given Hence idle phase implementation indicatability indicator inertial delay inherent function initial interconnection interface isotonous logical loop marked graph marking modelling circuit modules obtained operational cycle PAFC pair parallel Petri nets phase signal pipeline register protocol realized reset respect result Section self-synchronizing code self-timed semi-modular circuit sequence sequential circuits shown in Fig signal graph situations spacer speed-independent state-transition diagram structure stuck-at faults switching symbols T-flip-flop takeover techniques theorem token totally self-checking totally sequential transient transition a-b transition diagram transition process values variables w-class